`include "CPU.v"
`include "RAM.v"
`include "ROM.v"
`timescale 1ns / 100ps

module Top (
	input clk
);

	wire [9:0] ram_addr;
	wire [31:0] ram_read_data;
	wire [31:0] ram_write_data;
	wire ram_write_enable;

	wire [9:0] instruction_addr;
	wire [31:0] instruction;

	CPU inst_CPU (
			.clk              (clk),
			.ram_read_data    (ram_read_data),
			.instruction      (instruction),

			.ram_addr         (ram_addr),
			.ram_write_data   (ram_write_data),
			.ram_write_enable (ram_write_enable),
			.instruction_addr (instruction_addr)
		);

	ROM inst_ROM (
			.address(instruction_addr),

			.data(instruction)
		);

	RAM inst_RAM (
			.address      (ram_addr),
			.data_in      (ram_write_data),
			.write_enable (ram_write_enable),
			.clk          (clk),

			.data_out     (ram_read_data)
		);

endmodule